Waylon Cude
ec6ce08b21
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34 lines
1.2 KiB
Systemverilog
34 lines
1.2 KiB
Systemverilog
module pwm(
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input logic clk, reset,
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// Load control signal, if this is high we should load a new sample
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input logic load,
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// The audio sample to play back
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input logic [15:0] sample,
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// The audio output pin
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output wire pwm_pin
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);
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// What I imagine is that the counter here can be incremented each clock.
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// If the counter value is less than or equal to the value in the sample buffer
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// then you should turn on the PWM output. Otherwise if the counter is greater
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// than the value in the sample buffer the output will be off.
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//
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// This means that for small sample values the output will be enabled for only
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// short periods of time, exactly what we want.
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logic [15:0] pulse_counter;
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// A buffer to hold the sample in. Every clock cycle you should check load
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// to see if you should pull the sample off the bus and store it in here.
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logic [15:0] sample_buffer;
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// A control signal for driving the PWM high or low. This gets translated into
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// either a 'z or a '0 later as the PWM requires.
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logic should_output;
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// NOTE: tristating the pwm pin with a 'z will output a 1
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// sending a 0 will pull the pin to 0 as usual
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assign pwm_pin = should_output ? 'z : '0;
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endmodule
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