Waylon Cude
e32563131f
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104 lines
2.2 KiB
Systemverilog
104 lines
2.2 KiB
Systemverilog
module send_command(
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input clk,
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// The crc should be clocked way faster than the sender
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input crc_clk,
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input reset,
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input start,
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input [5:0] command,
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input [31:0] arguments,
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output logic ready,
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output logic sd_cmd
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);
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logic [47:0] to_send;
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logic crc_start;
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wire crc_ready;
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logic [6:0] crc;
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logic [$clog2(48):0] counter;
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logic send_sd_cmd;
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enum logic [2:0] {READY, SEND_CRC, DELAY, WAIT_CRC, SEND_DATA} cur_state, next_state;
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// We theoretically could speed up sd card initialization by hardcoding the
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// CRCs for it, but wasting an extra couple of cycles at 400khz shouldn't
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// really matter
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crc_gen crcGen(crc_clk,reset,crc_start,to_send[47-:40],crc_ready,crc);
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// State transitions
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always_comb begin
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case (cur_state)
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READY:
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if (start)
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next_state = SEND_CRC;
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else
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next_state = READY;
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SEND_CRC:
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next_state = DELAY;
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DELAY:
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next_state = WAIT_CRC;
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WAIT_CRC:
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if (crc_ready)
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next_state = SEND_DATA;
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else
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next_state = WAIT_CRC;
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SEND_DATA:
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if (counter != 0)
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next_state = SEND_DATA;
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else
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next_state = READY;
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default:
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next_state = READY;
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endcase
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end
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assign sd_cmd = send_sd_cmd ? 'z : 0;
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assign ready = (cur_state == READY);
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// Sequential logic
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always_ff @(posedge clk) begin
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// Default to high-z
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send_sd_cmd <= 1;
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case (cur_state)
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READY:
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begin
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counter <= 48;
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end
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SEND_CRC:
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begin
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to_send <= {1'b0, 1'b1, command, arguments, 8'b1};
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crc_start <= 1;
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end
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DELAY:
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crc_start <= 0;
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WAIT_CRC:
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to_send[7:1] <= crc;
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SEND_DATA:
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begin
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counter <= counter - 1;
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send_sd_cmd <= to_send[counter-1];
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end
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default: ;
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endcase
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end
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always_ff @(posedge clk) begin
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if (reset) begin
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cur_state <= READY;
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counter <= 48;
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end
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else begin
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cur_state <= next_state;
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end
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end
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endmodule
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