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21 lines
482 B
Systemverilog
21 lines
482 B
Systemverilog
module Playback_Controller(
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// This clock should be reasonably slow
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input logic clk,
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input logic reset,
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// Play and pause are the same button
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input logic play,
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input logic ff,
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// Output is 0, 1x, 2x, 4x, or 8x
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output wire [3:0] speed
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);
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wire play_pulse,ff_pulse;
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// NOTE: These might need to be hooked to an even lower clock? Not sure
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debouncer playDebouncer (clk,reset,play,play_pulse);
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debouncer ffDebouncer (clk,reset,ff,ff_pulse);
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endmodule
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