Waylon Cude
dff929de84
This module needs way reworked to just be a state machine. I was trying to get way too tricky with it so I went back to the drawing board and made a state machine diagram for it. The diagram is included with this commit. I also moved the current collection of documentation to a doc/ folder, and added a second-long audio rom to test everything out once the rom_sd is working.
104 lines
3.4 KiB
Systemverilog
104 lines
3.4 KiB
Systemverilog
// A dummy sdcard module for testing the audio port
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module sd(
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input logic clk,
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input logic reset,
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output logic ready,
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audio_buffer_interface.driver audio_buffer
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);
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// First we write 2048B into the memory buffer, then signal to play it and
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// wait for half signal to avoid overwriting memory
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logic initializing;
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logic [16:0] rom_address;
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logic [7:0] rom_data;
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logic rom_enable;
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// Keep track of pipeline delay so we don't write garbage into the buffer
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logic delay;
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// Keep track of if we are caught up to the buffer or not
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logic waiting;
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//TODO: This probably could be an assign, not sure
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assign ready = '1;
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always_ff @(posedge clk) begin
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if (reset) begin
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delay <= 1;
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rom_address <= 0;
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initializing <= 1;
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audio_buffer.addra <= 0;
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audio_buffer.ena <= 0;
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end
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else if (initializing) begin
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rom_enable <= 1;
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case (delay)
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1: delay <= 0;
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0: begin
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rom_address <= 1;
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delay <= 0;
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initializing <= 0;
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end
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endcase
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end
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else begin
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if (!waiting) begin
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audio_buffer.ena <= 1;
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audio_buffer.dina <= rom_data;
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audio_buffer.addra <= audio_buffer.addra + 1;
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end
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end
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end
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// xpm_memory_sprom: Single Port ROM
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// Xilinx Parameterized Macro, version 2024.2
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// The ROM has 17 address bits and 8 data bits to store 128KiB, more than
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// enough for one second of 48khz audio
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xpm_memory_sprom #(
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.ADDR_WIDTH_A(17), // DECIMAL
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.AUTO_SLEEP_TIME(0), // DECIMAL
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.CASCADE_HEIGHT(0), // DECIMAL
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.ECC_BIT_RANGE("7:0"), // String
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.ECC_MODE("no_ecc"), // String
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.ECC_TYPE("none"), // String
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.IGNORE_INIT_SYNTH(0), // DECIMAL
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.MEMORY_INIT_FILE("roundabout.mem"), // String
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.MEMORY_INIT_PARAM("0"), // String
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.MEMORY_OPTIMIZATION("true"), // String
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.MEMORY_PRIMITIVE("auto"), // String
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.MEMORY_SIZE(131072*8), // DECIMAL
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.MESSAGE_CONTROL(0), // DECIMAL
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.RAM_DECOMP("auto"), // String
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.READ_DATA_WIDTH_A(8), // DECIMAL
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.READ_LATENCY_A(2), // DECIMAL
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.READ_RESET_VALUE_A("0"), // String
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.RST_MODE_A("SYNC"), // String
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.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
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.USE_MEM_INIT(1), // DECIMAL
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.USE_MEM_INIT_MMI(0), // DECIMAL
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.WAKEUP_TIME("disable_sleep") // String
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)
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xpm_memory_sprom_inst (
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.douta(rom_data), // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
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.addra(rom_address), // ADDR_WIDTH_A-bit input: Address for port A read operations.
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.clka(clk), // 1-bit input: Clock signal for port A.
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.ena(rom_enable), // 1-bit input: Memory enable signal for port A. Must be high on clock
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// cycles when read operations are initiated. Pipelined internally.
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.rsta(reset) // 1-bit input: Reset signal for the final port A output register stage.
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// Synchronously resets output port douta to the value specified by
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// parameter READ_RESET_VALUE_A.
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);
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// End of xpm_memory_sprom_inst instantiation
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endmodule
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