Waylon Cude
7980424dc8
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ci/woodpecker/push/test-workflow Pipeline was successful
I think I did some funny math errors so new goal is 8-bit pcm
156 lines
4.1 KiB
Systemverilog
156 lines
4.1 KiB
Systemverilog
`ifdef VERILATOR
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`include "sdvd_defs.sv"
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`endif
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module rom_sd_tb;
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bit clk,reset;
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wire ready;
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int errors;
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logic [10:0] i;
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audio_buffer_interface buffer();
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rom_sd #("consecutive.mem") dut (clk,reset,ready,buffer.driver);
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initial forever #10 clk = ~clk;
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initial begin
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reset = 1;
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buffer.address_half = 0;
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@(posedge clk);
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reset = 0;
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// Audio data should not be flowing yet
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#1 assert (buffer.dina == 0)
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else begin
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errors++;
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$error("Data not zero after reset, found 0x%x",buffer.dina);
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end
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repeat (3) @(posedge clk);
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for (i = 0; i < 1024;) begin
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@(posedge clk);
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#1
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assert (buffer.addra === i)
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else begin
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errors++;
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$error("Incorrect address, expected %x found %x",i,buffer.addra);
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end
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assert (buffer.dina === ((i + 1) % 256))
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else begin
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errors++;
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$error("Incorrect data, expected 0x%x but found 0x%x",i[7:0],buffer.dina);
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end
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assert (i == 0 || buffer.ena === 1)
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else begin
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$error("Enable not high");
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errors++;
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end
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assert (buffer.address_half == 0)
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else begin
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errors++;
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$error("Incorrect address half, expected 0 but found %d",buffer.address_half);
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end
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i = i + 1;
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end
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// Wait a cycle for the buffer to catch up
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@(posedge clk);
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// Make sure that we start waiting and that we signal that the buffer
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// is ready
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#1 assert(buffer.ena === 0)
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else begin
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errors++;
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$error("Buffer did not wait after first full cycle");
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end
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assert(ready === 1)
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else begin
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errors++;
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$error("Buffer did not signal ready");
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end
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assert(dut.buffer_half === 1)
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else begin
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errors++;
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$error("Buffer half did not correctly change to 1");
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end
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// Set the address half high so we can test waiting/catching up to the
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// buffer
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buffer.address_half = 1;
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repeat (100) @(posedge clk);
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#1 assert(buffer.ena === 0)
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else begin
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errors++;
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$error("Buffer did not wait after first full cycle");
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end
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buffer.address_half = 0;
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repeat (3) @(posedge clk);
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// Check that sending into the upper half of the buffer works as
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// expected
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while (i != 0) begin
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@(posedge clk);
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#1
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assert (buffer.addra === i)
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else begin
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errors++;
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$error("Incorrect address, expected %x found %x",i,buffer.addra);
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end
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assert (buffer.dina === ((i + 1) % 256))
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else begin
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errors++;
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$error("Incorrect data, expected 0x%x but found 0x%x",i[7:0],buffer.dina);
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end
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assert (i == 0 || buffer.ena === 1)
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else begin
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$error("Enable not high");
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errors++;
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end
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assert (buffer.address_half == 0)
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else begin
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errors++;
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$error("Incorrect address half, expected 0 but found %d",buffer.address_half);
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end
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i = i + 1;
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end
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// Wait a cycle for the buffer to catch up
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@(posedge clk);
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// Make sure that we start waiting
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#1 assert(buffer.ena === 0)
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else begin
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errors++;
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$error("Buffer did not wait after second full cycle");
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end
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assert(ready === 1)
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else begin
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errors++;
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$error("Buffer did not signal ready");
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end
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assert(dut.buffer_half === 0)
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else begin
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errors++;
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$error("Buffer half did not correctly change to 0");
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end
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$display("Found %0d errors while testing rom_sd",errors);
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$finish;
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end
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endmodule
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