Waylon Cude
831e588986
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Hopefully this is enough of the project files for this to work ...
24 lines
432 B
Systemverilog
24 lines
432 B
Systemverilog
//NOTE: you should drive this with a slow clock to actually debounce input
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module Debouncer(input logic clk, input reset, input source, output wire out);
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logic pressed;
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assign out = pressed;
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always_ff @(posedge clk) begin
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if (reset)
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pressed <= 0;
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else if (!pressed && source)
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pressed <= 1;
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else if (pressed && !source)
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pressed <= 0;
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end
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//always_ff (@posedge clk) begin
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//
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//end
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endmodule
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