Waylon Cude
35cb264b26
All checks were successful
ci/woodpecker/push/test-workflow Pipeline was successful
We have something at least, audio is working and sounding dang good
26 lines
517 B
Systemverilog
26 lines
517 B
Systemverilog
module modular_clock_gen(
|
|
input clk, reset,
|
|
output logic oclk
|
|
);
|
|
parameter DIVISOR;
|
|
|
|
logic [$clog2(DIVISOR)-1:0] counter;
|
|
|
|
// clock will be high for about half of the cycle, depending on integer
|
|
// rounding
|
|
// OOPS this makes it combinational
|
|
//assign oclk = counter < (DIVISOR/2);
|
|
|
|
always_ff @(posedge clk) begin
|
|
if (reset)
|
|
counter <= DIVISOR-1;
|
|
else if (counter == 0)
|
|
counter <= DIVISOR-1;
|
|
else
|
|
counter <= counter - 1;
|
|
|
|
oclk <= counter < (DIVISOR/2);
|
|
end
|
|
|
|
endmodule
|