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The audio output is still messed up, but this commit gets everything as ready as it can get. Fixed up all the testbenches and added state machines for everything
81 lines
1.6 KiB
Systemverilog
81 lines
1.6 KiB
Systemverilog
`timescale 1ns / 1ps
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`ifdef VERILATOR
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`include "assertion_error.sv"
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`endif
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import assertion_error::errors;
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module debouncer_tb;
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parameter TESTCYCLES=1000;
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logic clk,reset,source;
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wire out;
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debouncer Dut (.*);
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bind debouncer debouncer_assertions AssertDut (.*);
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initial begin
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clk = 0;
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forever #10 clk = ~clk;
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end
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initial begin
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// Turn assertions off during reset
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$assertoff;
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$display("Testing debouncer");
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reset = 1;
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source = 0;
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@(posedge clk);
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@(posedge clk);
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reset = 0;
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$asserton;
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@(posedge clk);
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source = 1;
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#1;
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assert (out == 1) else begin
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$error("Output not brought high during first press");
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errors++;
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end
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@(posedge clk);
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#1;
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assert (out == 0) else begin
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$error("Output not brought low after first press");
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errors++;
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end
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@(posedge clk);
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source = 0;
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@(posedge clk);
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source = 1;
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#1;
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assert (out == 1) else begin
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$error("Output not brought high during second press");
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errors++;
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end
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@(posedge clk);
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source = 0;
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@(posedge clk);
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#1;
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assert (out == 0) else begin
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$error("Output not brought low after second press");
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errors++;
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end
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@(posedge clk);
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@(posedge clk);
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$display("Generating random input to test assertions");
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for (int i=0; i<TESTCYCLES; i++) begin
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source = $urandom;
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@(posedge clk);
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end
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if (errors == 0)
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$display("Found no errors while testing debouncer");
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else
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$display("ERROR: Found %0d errors while testing debouncer", errors);
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$finish;
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end
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endmodule
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