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This adds some unnecessary stuff into the debug core that I used to troubleshoot. There are like 5 bugfixes here. Especially of note is the low freq clock gen, I was trying to use modulo like you would do in a computer program but it was too slow, so I had to move the logic around a bunch.
71 lines
1.8 KiB
Systemverilog
71 lines
1.8 KiB
Systemverilog
`include "sdvd_defs.sv"
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import sdvd_defs::SPEED;
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module nexys_a7_top(
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input logic CLK100MHZ, CPU_RESETN,
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input logic BTNC, BTNR,
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output logic CA,CB,CC,CD,CE,CF,CG,
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output logic [7:0] AN
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);
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// Active high reset
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wire reset;
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assign reset = ~CPU_RESETN;
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logic clk_1khz, clk_10hz;
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logic seconds_pulse;
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SPEED speed;
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// Map C{A-G} to an array of 7-segment displays
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wire [6:0] segments [7:0];
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wire [2:0] segment_mux_select;
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// These segments are currently unused
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assign segments[7] = 0;
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assign segments[6] = 0;
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assign {CA,CB,CC,CD,CE,CF,CG} = ~segments[segment_mux_select];
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logic [$clog2(60)-1:0] seconds;
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logic [$clog2(60)-1:0] minutes;
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logic [$clog2(60)-1:0] hours;
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low_freq_clock_gen clockGen(CLK100MHZ, reset, speed, clk_1khz, clk_10hz, seconds_pulse);
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// Count the number on seconds, hours, and minutes elapsed
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// If the speed is faster this will pulse more often than once a second
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// but will still theoretically be a second of video time
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always_ff @(posedge seconds_pulse) begin
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if (reset) begin
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seconds <= 0;
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minutes <= 0;
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hours <= 0;
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end
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else if (seconds == 59) begin
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seconds <= 0;
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if (minutes == 59) begin
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minutes <= 0;
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hours <= hours + 1;
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end
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else
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minutes <= minutes + 1;
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end
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else
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seconds <= seconds + 1;
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end
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display_anode_driver anodeDriver(clk_1khz,reset,AN,segment_mux_select);
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seconds_display secondsSegment (seconds, segments[1], segments[0]);
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seconds_display minutesSegment (minutes, segments[3], segments[2]);
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seconds_display hoursSegment (hours, segments[5], segments[4]);
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// Run the playback speed state machine at a lower rate
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// Gets rid of button bouncing
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playback_controller playbackController (clk_10hz,reset,BTNC, BTNR, speed);
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endmodule
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