This module needs way reworked to just be a state machine. I was trying to get way too tricky with it so I went back to the drawing board and made a state machine diagram for it. The diagram is included with this commit. I also moved the current collection of documentation to a doc/ folder, and added a second-long audio rom to test everything out once the rom_sd is working.
24 lines
770 B
Plaintext
24 lines
770 B
Plaintext
digraph rom_sd {
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Reset [shape = doublecircle, label = "RESET\nbuffer_half = 0\nrom_address = 0\nrom_enable = 1\nbuf.addr=0\nready=0"];
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node [shape = circle];
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Delay [label="DELAY\nrom_address++"];
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WriteBuf [label="WRITEBUF\nbuf.ena=1\nbuf.data=rom_data\nbuf.addr++\nrom_addr++"];
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EndWrite [label="ENDWRITE\nbuf.ena=1\nbuf.data=rom_data\nbuf.addr++\nready=1"];
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Wait [label = "WAIT\nbuf.ena=0"];
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Reset -> Reset [label="reset"];
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Reset -> Delay [label="!reset"];
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Delay -> WriteBuf;
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WriteBuf -> WriteBuf [label="buf.addr < 1023"]
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WriteBuf -> EndWrite [label="buf.addr == 1023"]
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EndWrite -> Wait;
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Wait -> Wait [label = "buffer_half == buf.address_half"]
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Wait -> Delay [label = "buffer_half != buf.address_half"]
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}
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