## Bugs I Found

### Audio Buffer
- Forgot to assign to a delay counter

### Debouncer
- Logic was fundamentally wrong
- Found multiple logic bugs with testbench and then assertions

### Display Converter
- Found a typo in a single digit

### Low Freq Clock Gen
- Was initially trying to do modulo at max clock speed, failing timing


### sd_rom
- ROM was getting totally optimized out and was doing nothing in simulation, and
  didn't show up in synthesized design
- Timing issues, ROM was one cycle slower than expected, latching takes an extra
  cycle too, had to rework state machines, there are a bonus 2 delay states when
  starting and ending writes

### PWM
- major design problems
- clocked too slow
- initial goal of 16-bit audio isn't feasible because 100MHz isn't fast enough
  to pwm based on a 16-bit counter, would give a sample rate of 1.5khz

### command_sender
- output ready signal was delay a cycle because it was set by sequential logic,
  detected in testing, changed it to a combinational output for 1 cycle speedup
- counter was being set in multiple blocks, caught by synthesis
- output phase too long, caught in hw

### read_command
- response_type was not getting correctly stored/set, breaking the module
  entirely. Detected in testbench
- off-by-one error detected in the counter

## read_data
- audio buffer address to write to was never changing, caught in simulation
- some off-by-one errors in the byte shifting were found and corrected

### modular_clock
- stopped ticking on reset
- meant that every module using these clocks w/ a synchronous reset would get
  stuck and never reset
- found during hw debugging