module modular_clock_gen(
    input clk, reset,
    output logic oclk
);
parameter DIVISOR;

logic [$clog2(DIVISOR)-1:0] counter;

logic set;

// clock will be high for about half of the cycle, depending on integer
// rounding
// OOPS this makes it combinational
//assign oclk = counter < (DIVISOR/2);

always_ff @(posedge clk) begin
    // modular clock has to keep ticking through reset
    // so everything with a synchronous reset actually works
    if (reset && !set) begin
        counter <= DIVISOR-1;
        set <= 1;
    end
    else if (counter == 0)
        counter <= DIVISOR-1;
    else 
        counter <= counter - 1;

    oclk <= counter < (DIVISOR/2);
end

endmodule