`include "sdvd_defs.sv"
import sdvd_defs::SPEED;
// Takes in a 100MHz clock and generates the very low freq signals needed
// for driving the control logic
module low_freq_clock_gen(
    input logic clk, reset,
    input SPEED speed,
    output logic clk1k, clk10h, seconds_pulse
);

logic [$clog2(100_000_000):0] counter;
logic [$clog2(4000):0] seconds_counter;
logic clk4k;

assign clk1k = (counter % (100_000_000/1000)) != 0;
assign clk10h = (counter % (100_000_000/10)) != 0;
assign clk4k = (counter % (100_000_000/4000)) != 0;

always_ff @(posedge clk) begin
    // NOTE: This generates a pulse on the same clock cycle that reset is
    // asserted. Is that bad??
    if (reset)
        counter <= 0;
    // Roll the counter over back to zero every second
    else if (counter == 99_999_999)
        counter <= 0;
    else
        counter <= counter + 1;

    // This logic handles the variable-speed seconds counter
    if (reset) begin
        seconds_pulse <= 0;
        seconds_counter <= 0;
    end
    else if (clk4k && seconds_counter >= 4000) begin
        seconds_counter <= seconds_counter-4000;
        seconds_pulse <= 1;
    end
    else if (clk4k) begin
        seconds_pulse <= 0;
        seconds_counter <= seconds_counter + {9'b0, speed};
    end
end

endmodule