module modular_clock_gen(
    input clk, reset,
    output oclk
);
parameter DIVISOR;

logic [$clog2(DIVISOR)-1:0] counter;

// clock will be high for about half of the cycle, depending on integer
// rounding
assign oclk = counter < (DIVISOR/2);

always_ff @(posedge clk) begin
    if (reset)
        counter <= DIVISOR-1;
    else if (counter == 0)
        counter <= DIVISOR-1;
    else 
        counter <= counter - 1;
end

endmodule