// NOTE: This expects to be driven with a 100khz clock
module display_anode_driver(
    input logic clk, 
    input logic reset, 
    output logic [7:0] AN, 
    output logic [2:0] mux_select);

// This is just a shift register that drives each anode individually
always_ff @(posedge clk) begin
    if (reset) begin
        AN <= '1 - 1;
        mux_select <= 0;
    end
    else begin
        AN <= {AN[6:0], AN[7]};
        // Letting this overflow will automatically reset it
        mux_select <= mux_select + 1;
    end
end
endmodule