module send_command_tb;

bit clk;
// The crc should be clocked way faster than the sender
bit crc_clk;
logic reset;
logic start;
logic [5:0] command;
logic [31:0] arguments;
wire ready;
wire sd_cmd;

logic [47:0] fill_me;
int counter;

logic sd_cmd_real;

assign sd_cmd_real = (sd_cmd === 'z) ? 1 : 0;

send_command dut(.*);

initial forever #100 clk = ~clk;
initial forever #20 crc_clk = ~crc_clk;



initial begin
    reset = 1;
    start = 0;

    repeat (2) @(posedge clk);

    reset = 0;
    @(posedge clk);

    start = 1;
    command = 8;
    arguments = 'h1AA;

    counter = 48;

    @(posedge clk);
    start = 0;

    // Try receiving the CMD8
    while (counter != 0) begin
        // Check for the start bit, or that we're receiving a message
        if (sd_cmd_real != 1 || counter != 48) begin
            fill_me = {fill_me[46:0], sd_cmd_real};
            counter--;
        end
        @(posedge clk);
    end

    assert (fill_me === {2'b01, 6'd8, 32'h1AA, 8'h87})
        else $error("Received wrong command, got 0x%x",fill_me);

    repeat (1) @(posedge clk);
    assert (ready)
        else $error("SD command sender not ready");

    repeat (10) @(posedge clk);

    $finish;
end
endmodule