/*****
 * pwm_tb.sv - testbench for the pwm.sv module. 
 *
 * @author: Dilanthi Prentice, Waylon Cude
 * @date: 6/12/2025
 * */

module pwm_tb;
    bit clk, reset;

    logic load;
    wire pwm_pin;
    logic [15:0] sample;

    pwm #(16) dut (.*);

    initial forever #10 clk = ~clk;

    initial begin
        reset = 1;
        @(posedge clk);
        @(posedge clk);
        reset = 0;
        load = 1;
        sample = 0;
        for (int i=0; i < (1<<16)-1; i++) begin
            @(posedge clk) assert (pwm_pin === 0)
                else $error("Should be low at %d",i);
        end
        reset = 0;
        load = 1;
        sample = '1;
        @(posedge clk)
        for (int i=0; i < (1<<16)-1; i++) begin
            @(posedge clk) assert (pwm_pin === 'z)
                else $error("Should be high at %d",i);
        end

        reset = 0;
        load = 1;
        // Should be about half on
        sample = 1<<15;
        @(posedge clk)
        for (int i=0; i < (1<<15); i++) begin
            @(posedge clk) assert (pwm_pin === 'z) 
                else $error("Should be high at %d",i);
        end
        sample = 1<<15;
        for (int i = (1  << 15); i < (1<<16)-1; i++) begin
            @(posedge clk) assert (pwm_pin === 0)
                else $error("Should be low at %d",i);
        end
        $finish;

    end

endmodule