From ec6ce08b217939158cbe0c00fbebe79a6c8dd808 Mon Sep 17 00:00:00 2001
From: Waylon Cude <waylon.cude@finzdani.net>
Date: Thu, 22 May 2025 20:26:29 -0700
Subject: [PATCH] Add stubbed out pwm implementation

---
 design/audio/pwm.sv | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)
 create mode 100644 design/audio/pwm.sv

diff --git a/design/audio/pwm.sv b/design/audio/pwm.sv
new file mode 100644
index 0000000..4fea8eb
--- /dev/null
+++ b/design/audio/pwm.sv
@@ -0,0 +1,33 @@
+module pwm(
+    input logic clk, reset,
+    // Load control signal, if this is high we should load a new sample
+    input logic load,
+    // The audio sample to play back
+    input logic [15:0] sample,
+    // The audio output pin
+    output wire pwm_pin
+);
+
+// What I imagine is that the counter here can be incremented each clock.
+// If the counter value is less than or equal to the value in the sample buffer
+// then you should turn on the PWM output. Otherwise if the counter is greater
+// than the value in the sample buffer the output will be off.
+//
+// This means that for small sample values the output will be enabled for only
+// short periods of time, exactly what we want.
+logic [15:0] pulse_counter;
+
+// A buffer to hold the sample in. Every clock cycle you should check load
+// to see if you should pull the sample off the bus and store it in here.
+logic [15:0] sample_buffer;
+
+// A control signal for driving the PWM high or low. This gets translated into
+// either a 'z or a '0 later as the PWM requires.
+logic should_output;
+
+// NOTE: tristating the pwm pin with a 'z will output a 1
+//       sending a 0 will pull the pin to 0 as usual
+assign pwm_pin = should_output ? 'z : '0;
+
+
+endmodule