Initial work on rom_sd

This module needs way reworked to just be a state machine. I was trying
to get way too tricky with it so I went back to the drawing board and
made a state machine diagram for it. The diagram is included with this
commit. I also moved the current collection of documentation to a doc/
folder, and added a second-long audio rom to test everything out once
the rom_sd is working.

doc/bugs.md

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+## Bugs I Found
+
+### Audio Buffer
+- Forgot to assign to a delay counter
+
+### Debouncer
+- Logic was fundamentally wrong
+- Found multiple logic bugs with testbench and then assertions
+
+### Display Converter
+- Found a typo in a single digit
+
+### Low Freq Clock Gen
+- Was initially trying to do modulo at max clock speed, failing timing

doc/modules.md

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+## Planned Modules
+
+- SD Card Reader
+
+- VGA Controller
+  - Not sure if the framebuffer is here or in RAM?
+  - Each pixel is 12-bits
+  - Probably fit into 16-bit words in RAM?
+  - Plan on 640x480
+  - Should we do double buffering?
+
+- Audio Controller
+  - Again, not sure how the buffer will work. Might just take in 1KiB as a
+    verilog array?
+
+- Control logic
+  - Play
+  - Pause
+  - Volume up/down
+  - Fast forward
+    - Maybe start at 2x, then go to 4x then 8x with more presses?
+  - Rewind, maybe, it's real hard though
+
+- DRAM/SRAM controller
+  - We might need this for buffering frames? Not sure if we implicitly can use
+    SRAM with verilog arrays
+  - The SRAM interface is easier but slower
+  - Hopefully we don't need this but who knows
+
+- 8 segment display driver
+  - Takes in a play time in seconds and displays it in hour:minute:second
+  - Maybe could take in seconds, minutes, and hours separately?
+    - This would save us from having to do modulo
+    - It'd be easy to check if seconds == 60 and then increment minutes
+

doc/rom_sd.gv

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+digraph rom_sd {
+    Reset [shape = doublecircle, label = "RESET\nbuffer_half = 0\nrom_address = 0\nrom_enable = 1\nbuf.addr=0\nready=0"];
+    node [shape = circle];
+    Delay [label="DELAY\nrom_address++"];
+    WriteBuf [label="WRITEBUF\nbuf.ena=1\nbuf.data=rom_data\nbuf.addr++\nrom_addr++"];
+    EndWrite [label="ENDWRITE\nbuf.ena=1\nbuf.data=rom_data\nbuf.addr++\nready=1"];
+    Wait [label = "WAIT\nbuf.ena=0"];
+
+    Reset -> Reset [label="reset"];
+    Reset -> Delay [label="!reset"];
+
+    Delay -> WriteBuf;
+
+    WriteBuf -> WriteBuf [label="buf.addr < 1023"]
+    WriteBuf -> EndWrite [label="buf.addr == 1023"]
+
+    EndWrite -> Wait;
+
+    Wait -> Wait [label = "buffer_half == buf.address_half"]
+    Wait -> Delay [label = "buffer_half != buf.address_half"]
+
+
+}