Initial work on rom_sd

This module needs way reworked to just be a state machine. I was trying
to get way too tricky with it so I went back to the drawing board and
made a state machine diagram for it. The diagram is included with this
commit. I also moved the current collection of documentation to a doc/
folder, and added a second-long audio rom to test everything out once
the rom_sd is working.

design/audio/audio_buffer.sv

@@ -12,9 +12,6 @@ module audio_buffer(
     input logic play, stop,
     input SPEED speed,
 
-    // Whether the current address being read from is in the upper or lower
-    // half of the 2KiB buffer
-    output logic address_half,
 
     // Whether the audio buffer is currently playing
     output logic playing,
@@ -23,11 +20,13 @@ module audio_buffer(
     output logic [15:0] sample,
 
     // Inputs for the memory buffer
-    input logic [10:0] addra,
-    input logic [7:0] dina,
-    input logic clka, ena
+    audio_buffer_interface.receiver driver
 );
 
+// Whether the current address being read from is in the upper or lower
+// half of the 2KiB buffer
+let address_half = driver.address_half;
+
 logic [9:0] address;
 
 // State register
@@ -117,16 +116,16 @@ xpm_memory_sdpram #(
 )
 buffer (
   .doutb(doutb),          // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
-  .addra(addra),          // ADDR_WIDTH_A-bit input: Address for port A write operations.
+  .addra(driver.addra),          // ADDR_WIDTH_A-bit input: Address for port A write operations.
   .addrb(address),        // ADDR_WIDTH_B-bit input: Address for port B read operations.
-  .clka(clka),            // 1-bit input: Clock signal for port A. Also clocks port B when
+  .clka(driver.clka),            // 1-bit input: Clock signal for port A. Also clocks port B when
                           // parameter CLOCKING_MODE is "common_clock".
 
   .clkb(clk),             // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
                           // "independent_clock". Unused when parameter CLOCKING_MODE is
                           // "common_clock".
-  .dina(dina),            // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
-  .ena(ena),              // 1-bit input: Memory enable signal for port A. Must be high on clock
+  .dina(driver.dina),            // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
+  .ena(driver.ena),              // 1-bit input: Memory enable signal for port A. Must be high on clock
                           // cycles when write operations are initiated. Pipelined internally.
 
   .enb(enb),              // 1-bit input: Memory enable signal for port B. Must be high on clock
@@ -135,7 +134,7 @@ buffer (
   .rstb(reset),            // 1-bit input: Reset signal for the final port B output register stage.
                           // Synchronously resets output port doutb to the value specified by
                           // parameter READ_RESET_VALUE_B.
-  .wea(ena)               // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
+  .wea(driver.ena)               // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
                           // for port A input data port dina. 1 bit wide when word-wide writes are
                           // used. In byte-wide write configurations, each bit controls the
                           // writing one byte of dina to address addra. For example, to