Merge branch 'master' into comment_clean_up

design/audio/audio_buffer.sv

@@ -34,11 +34,14 @@ module audio_buffer(
     // Inputs for the memory buffer
     audio_buffer_interface.receiver driver
 );
-logic [9:0] address;
+// Size of samples, 8bit or 16bit supported
+parameter SIZE=16;
+(* MARK_DEBUG = "TRUE" *)
+logic [11-(SIZE/8):0] address;
 
 // State register
 logic enb;
-logic [15:0] doutb;
+logic [(SIZE-1):0] doutb;
 
 // A single bit counter, to avoid feeding samples given the 1 cycle read delay
 logic delay;
@@ -47,7 +50,7 @@ logic delay;
 // half of the 2KiB buffer
 //
 // The MSB of the address == higher/lower half address
-assign driver.address_half = address[9];
+assign driver.address_half = address[11-(SIZE/8)];
 
 always_ff @(posedge clk) begin
     enb <= 0;
@@ -76,7 +79,7 @@ always_ff @(posedge clk) begin
             address <= address + speed;
             enb <= 1;
             if (delay == 0) begin
-                sample <= doutb;
+                sample[15-:SIZE] <= doutb;
             end
             else begin
                 sample <= '0;
@@ -90,7 +93,7 @@ end
 //vivado block ram xpm macro
 xpm_memory_sdpram #(
   .ADDR_WIDTH_A(11),                    // DECIMAL
-  .ADDR_WIDTH_B(10),                    // DECIMAL
+  .ADDR_WIDTH_B(12-(SIZE/8)),           // DECIMAL
   .AUTO_SLEEP_TIME(0),                  // DECIMAL
   .BYTE_WRITE_WIDTH_A(8),               // DECIMAL
   .CASCADE_HEIGHT(0),                   // DECIMAL
@@ -106,7 +109,7 @@ xpm_memory_sdpram #(
   .MEMORY_SIZE(16*1024),                // DECIMAL
   .MESSAGE_CONTROL(0),                  // DECIMAL
   .RAM_DECOMP("auto"),                  // String
-  .READ_DATA_WIDTH_B(16),               // DECIMAL
+  .READ_DATA_WIDTH_B(SIZE),             // DECIMAL
   .READ_LATENCY_B(1),                   // DECIMAL
   .READ_RESET_VALUE_B("0"),             // String
   .RST_MODE_A("SYNC"),                  // String

design/audio/pwm.sv

@@ -21,6 +21,7 @@ module pwm(
 parameter DEPTH=11;
 
 logic [DEPTH-1:0] pulse_counter;
+(* MARK_DEBUG = "TRUE" *)
 logic [15:0] sample_buffer;
 logic should_output;