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comment clean up

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dilanthi
2025-06-10 02:51:18 -07:00
parent 53b48c0bce
commit 9af830daa0
9 changed files with 93 additions and 63 deletions
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design/audio/audio_buffer.sv
+42 -45
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@@ -6,6 +6,9 @@
* @date: 6/12/2025
*
* */
//define used here because verilator needs it but vivado is smart enough
//not to.
`ifdef VERILATOR
`include "sdvd_defs.sv"
`endif
@@ -72,8 +75,6 @@ always_ff @(posedge clk) begin
// This will overflow to the correct value always
address <= address + speed;
enb <= 1;
// NOTE: I really don't know a good way to generate the load
// signal. It maybe could be an inverted 48khz clock?
if (delay == 0) begin
sample <= doutb;
end
@@ -86,59 +87,56 @@ always_ff @(posedge clk) begin
end
end
//xpm_memory_sdpram #(
// .WRITE_DATA_WIDTH_A(16)
//) buffer ();
//vivado block ram xpm macro
xpm_memory_sdpram #(
.ADDR_WIDTH_A(11), // DECIMAL
.ADDR_WIDTH_B(10), // DECIMAL
.AUTO_SLEEP_TIME(0), // DECIMAL
.BYTE_WRITE_WIDTH_A(8), // DECIMAL
.CASCADE_HEIGHT(0), // DECIMAL
.CLOCKING_MODE("independent_clock"), // String
.ECC_BIT_RANGE("7:0"), // String
.ECC_MODE("no_ecc"), // String
.ECC_TYPE("none"), // String
.IGNORE_INIT_SYNTH(0), // DECIMAL
.MEMORY_INIT_FILE("none"), // String
.MEMORY_INIT_PARAM("0"), // String
.MEMORY_OPTIMIZATION("true"), // String
.MEMORY_PRIMITIVE("auto"), // String
.MEMORY_SIZE(16*1024), // DECIMAL
.MESSAGE_CONTROL(0), // DECIMAL
.RAM_DECOMP("auto"), // String
.READ_DATA_WIDTH_B(16), // DECIMAL
.READ_LATENCY_B(1), // DECIMAL
.READ_RESET_VALUE_B("0"), // String
.RST_MODE_A("SYNC"), // String
.RST_MODE_B("SYNC"), // String
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
.USE_MEM_INIT(1), // DECIMAL
.USE_MEM_INIT_MMI(0), // DECIMAL
.WAKEUP_TIME("disable_sleep"), // String
.WRITE_DATA_WIDTH_A(8), // DECIMAL
.WRITE_MODE_B("no_change"), // String
.WRITE_PROTECT(1) // DECIMAL
.ADDR_WIDTH_A(11), // DECIMAL
.ADDR_WIDTH_B(10), // DECIMAL
.AUTO_SLEEP_TIME(0), // DECIMAL
.BYTE_WRITE_WIDTH_A(8), // DECIMAL
.CASCADE_HEIGHT(0), // DECIMAL
.CLOCKING_MODE("independent_clock"), // String
.ECC_BIT_RANGE("7:0"), // String
.ECC_MODE("no_ecc"), // String
.ECC_TYPE("none"), // String
.IGNORE_INIT_SYNTH(0), // DECIMAL
.MEMORY_INIT_FILE("none"), // String
.MEMORY_INIT_PARAM("0"), // String
.MEMORY_OPTIMIZATION("true"), // String
.MEMORY_PRIMITIVE("auto"), // String
.MEMORY_SIZE(16*1024), // DECIMAL
.MESSAGE_CONTROL(0), // DECIMAL
.RAM_DECOMP("auto"), // String
.READ_DATA_WIDTH_B(16), // DECIMAL
.READ_LATENCY_B(1), // DECIMAL
.READ_RESET_VALUE_B("0"), // String
.RST_MODE_A("SYNC"), // String
.RST_MODE_B("SYNC"), // String
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
.USE_MEM_INIT(1), // DECIMAL
.USE_MEM_INIT_MMI(0), // DECIMAL
.WAKEUP_TIME("disable_sleep"), // String
.WRITE_DATA_WIDTH_A(8), // DECIMAL
.WRITE_MODE_B("no_change"), // String
.WRITE_PROTECT(1) // DECIMAL
)
buffer (
.doutb(doutb), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
.addra(driver.addra), // ADDR_WIDTH_A-bit input: Address for port A write operations.
.addra(driver.addra), // ADDR_WIDTH_A-bit input: Address for port A write operations.
.addrb(address), // ADDR_WIDTH_B-bit input: Address for port B read operations.
.clka(driver.clka), // 1-bit input: Clock signal for port A. Also clocks port B when
.clka(driver.clka), // 1-bit input: Clock signal for port A. Also clocks port B when
// parameter CLOCKING_MODE is "common_clock".
.clkb(clk), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
// "independent_clock". Unused when parameter CLOCKING_MODE is
// "common_clock".
.dina(driver.dina), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
.ena(driver.ena), // 1-bit input: Memory enable signal for port A. Must be high on clock
.dina(driver.dina), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
.ena(driver.ena), // 1-bit input: Memory enable signal for port A. Must be high on clock
// cycles when write operations are initiated. Pipelined internally.
.enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on clock
// cycles when read operations are initiated. Pipelined internally.
//active high reset
.rstb(reset), // 1-bit input: Reset signal for the final port B output register stage.
.rstb(reset), // 1-bit input: Reset signal for the final port B output register stage.
// Synchronously resets output port doutb to the value specified by
// parameter READ_RESET_VALUE_B.
.wea(driver.ena), // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
@@ -147,11 +145,10 @@ buffer (
// writing one byte of dina to address addra. For example, to
// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
// is 32, wea would be 4'b0010.
// Extra inputs that I guess I need
.sleep(0),
.injectsbiterra(0),
.sleep(0), // The XPM macros say these can be removed, but when I did this the
.injectsbiterra(0), // entire block memory got optimized out. These were readded in later
.injectdbiterra(0),
// With a latency of 1 this surely does not matter
.regceb(enb)
);