More fixup on rom_sd

design/sd/rom_sd.sv

@@ -1,11 +1,11 @@
 // A dummy sdcard module for testing the audio port
 
-module sd(
+module rom_sd(
     input logic clk,
     input logic reset,
     output logic ready,
 
-    audio_buffer_interface.driver buffer
+    buffer_interface.driver buffer
 );
 
 // First we write 2048B into the memory buffer, then signal to play it and
@@ -14,45 +14,16 @@ logic initializing;
 logic [16:0] rom_addr;
 logic [7:0] rom_data;
 logic rom_enable;
-// Keep track of pipeline delay so we don't write garbage into the buffer
+logic buffer_half;
-logic delay;
 
-// Keep track of if we are caught up to the buffer or not
-logic waiting;
-//TODO: This probably could be an assign, not sure
-
-assign ready = '1;
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        delay <= 1;
         rom_addr <= 0;
         initializing <= 1;
-        audio_buffer.addra <= 0;
+        buffer.addra <= 0;
-        audio_buffer.ena <= 0;
+        buffer.ena <= 0;
     end
-    else if (initializing) begin
-        rom_enable <= 1;
-        case (delay)
-            1:  delay <= 0;
-            0:  begin
-                rom_addr <= 1;
-                delay <= 0;
-                initializing <= 0;
-                end
-        endcase
-    end
-    else begin
-        if (!waiting) begin
-            audio_buffer.ena <= 1;
-            audio_buffer.dina <= rom_data;
-            audio_buffer.addra <= audio_buffer.addra + 1;
-        end
-
-    end
-
-    
-
 end