diff --git a/SDVD.xpr b/SDVD.xpr
index b371300..fc10aaa 100644
--- a/SDVD.xpr
+++ b/SDVD.xpr
@@ -45,7 +45,7 @@
     <Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
     <Option Name="BoardPart" Val="digilentinc.com:nexys-a7-100t:part0:1.2"/>
     <Option Name="BoardPartRepoPaths" Val="$PPRDIR/../../../.Xilinx/Vivado/2024.2/xhub/board_store/xilinx_board_store"/>
-    <Option Name="ActiveSimSet" Val="sim_1"/>
+    <Option Name="ActiveSimSet" Val="seconds_display_tb"/>
     <Option Name="DefaultLib" Val="xil_defaultlib"/>
     <Option Name="ProjectType" Val="Default"/>
     <Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
@@ -61,7 +61,7 @@
     <Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
     <Option Name="EnableBDX" Val="FALSE"/>
     <Option Name="DSABoardId" Val="nexys-a7-100t"/>
-    <Option Name="WTXSimLaunchSim" Val="0"/>
+    <Option Name="WTXSimLaunchSim" Val="9"/>
     <Option Name="WTModelSimLaunchSim" Val="0"/>
     <Option Name="WTQuestaLaunchSim" Val="0"/>
     <Option Name="WTIesLaunchSim" Val="0"/>
@@ -99,7 +99,28 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/design/display_anode_driver.sv">
+      <File Path="$PPRDIR/design/segment_display/display_anode_driver.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/segment_display/display_converter.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/sdvd_defs.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <File Path="$PPRDIR/design/low_freq_clock_gen.sv">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -113,7 +134,7 @@
           <Attr Name="UsedIn" Val="simulation"/>
         </FileInfo>
       </File>
-      <File Path="$PPRDIR/design/seconds_display.sv">
+      <File Path="$PPRDIR/design/segment_display/seconds_display.sv">
         <FileInfo>
           <Attr Name="UsedIn" Val="synthesis"/>
           <Attr Name="UsedIn" Val="implementation"/>
@@ -147,6 +168,13 @@
     </FileSet>
     <FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
       <Filter Type="Srcs"/>
+      <File Path="$PPRDIR/verification/segment_display/seconds_display_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
       <File Path="$PPRDIR/verification/debouncer_tb.sv">
         <FileInfo>
           <Attr Name="AutoDisabled" Val="1"/>
@@ -157,9 +185,8 @@
       </File>
       <Config>
         <Option Name="DesignMode" Val="RTL"/>
-        <Option Name="TopModule" Val="nexys_a7_top"/>
+        <Option Name="TopModule" Val="seconds_display_tb"/>
         <Option Name="TopLib" Val="xil_defaultlib"/>
-        <Option Name="TopAutoSet" Val="TRUE"/>
         <Option Name="TransportPathDelay" Val="0"/>
         <Option Name="TransportIntDelay" Val="0"/>
         <Option Name="SelectedSimModel" Val="rtl"/>
@@ -179,6 +206,31 @@
         <Option Name="TopAutoSet" Val="TRUE"/>
       </Config>
     </FileSet>
+    <FileSet Name="seconds_display_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/seconds_display_tb" RelGenDir="$PGENDIR/seconds_display_tb">
+      <File Path="$PPRDIR/verification/segment_display/seconds_display_tb.sv">
+        <FileInfo>
+          <Attr Name="UsedIn" Val="synthesis"/>
+          <Attr Name="UsedIn" Val="implementation"/>
+          <Attr Name="UsedIn" Val="simulation"/>
+        </FileInfo>
+      </File>
+      <Config>
+        <Option Name="DesignMode" Val="RTL"/>
+        <Option Name="TopModule" Val="seconds_display_tb"/>
+        <Option Name="TopLib" Val="xil_defaultlib"/>
+        <Option Name="TransportPathDelay" Val="0"/>
+        <Option Name="TransportIntDelay" Val="0"/>
+        <Option Name="SelectedSimModel" Val="rtl"/>
+        <Option Name="PamDesignTestbench" Val=""/>
+        <Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
+        <Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
+        <Option Name="PamPseudoTop" Val="pseudo_tb"/>
+        <Option Name="SrcSet" Val="sources_1"/>
+        <Option Name="CosimPdi" Val=""/>
+        <Option Name="CosimPlatform" Val=""/>
+        <Option Name="CosimElf" Val=""/>
+      </Config>
+    </FileSet>
   </FileSets>
   <Simulators>
     <Simulator Name="XSim">
diff --git a/design/display_anode_driver.sv b/design/segment_display/display_anode_driver.sv
similarity index 100%
rename from design/display_anode_driver.sv
rename to design/segment_display/display_anode_driver.sv
diff --git a/design/display_converter.sv b/design/segment_display/display_converter.sv
similarity index 98%
rename from design/display_converter.sv
rename to design/segment_display/display_converter.sv
index acc9d8e..668410d 100644
--- a/design/display_converter.sv
+++ b/design/segment_display/display_converter.sv
@@ -21,7 +21,7 @@ localparam logic [6:0] segment_rom [0:ROM_SIZE-1] = '{
     7'b0000110, //1
     7'b1101101, //2
     7'b1111001, //3
-    7'b1011011, //4
+    7'b0110011, //4
     7'b1011011, //5
     7'b1011111, //6
     7'b1110000, //7
diff --git a/design/seconds_display.sv b/design/segment_display/seconds_display.sv
similarity index 100%
rename from design/seconds_display.sv
rename to design/segment_display/seconds_display.sv
diff --git a/verification/seconds_display_tb.sv b/verification/segment_display/seconds_display_tb.sv
similarity index 82%
rename from verification/seconds_display_tb.sv
rename to verification/segment_display/seconds_display_tb.sv
index 1a5e687..493d0bb 100644
--- a/verification/seconds_display_tb.sv
+++ b/verification/segment_display/seconds_display_tb.sv
@@ -1,3 +1,4 @@
+`timescale 1ns / 1ps
 module seconds_display_tb;
 int errors = 0;
 logic [5:0] seconds;
@@ -16,14 +17,16 @@ initial begin
         #1
         if (display_ones !== expected_ones) begin
             errors++;
-            $display("Failed ones test case, displayed = %b, expected = %b",
+            $error("Failed ones test case, seconds = %d, displayed = %b, expected = %b",
+                     seconds,
                      display_ones,
                      expected_ones);
         end
         else
         if (display_tens !== expected_tens) begin
             errors++;
-            $display("Failed tens test case, displayed = %b, expected = %b",
+            $error("Failed tens test case, seconds = %d, displayed = %b, expected = %b",
+                     seconds,
                      display_tens,
                      expected_tens);
         end