Fixup on rom_sd flowchart

design/sd/rom_sd.sv

@@ -5,13 +5,13 @@ module sd(
     input logic reset,
     output logic ready,
 
-    audio_buffer_interface.driver audio_buffer
+    audio_buffer_interface.driver buffer
 );
 
 // First we write 2048B into the memory buffer, then signal to play it and
 // wait for half signal to avoid overwriting memory
 logic initializing;
-logic [16:0] rom_address;
+logic [16:0] rom_addr;
 logic [7:0] rom_data;
 logic rom_enable;
 // Keep track of pipeline delay so we don't write garbage into the buffer
@@ -26,7 +26,7 @@ assign ready = '1;
 always_ff @(posedge clk) begin
     if (reset) begin
         delay <= 1;
-        rom_address <= 0;
+        rom_addr <= 0;
         initializing <= 1;
         audio_buffer.addra <= 0;
         audio_buffer.ena <= 0;
@@ -36,7 +36,7 @@ always_ff @(posedge clk) begin
         case (delay)
             1:  delay <= 0;
             0:  begin
-                rom_address <= 1;
+                rom_addr <= 1;
                 delay <= 0;
                 initializing <= 0;
                 end
@@ -87,7 +87,7 @@ xpm_memory_sprom #(
 )
 xpm_memory_sprom_inst (
   .douta(rom_data),                   // READ_DATA_WIDTH_A-bit output: Data output for port A read operations.
-  .addra(rom_address),                   // ADDR_WIDTH_A-bit input: Address for port A read operations.
+  .addra(rom_addr),                   // ADDR_WIDTH_A-bit input: Address for port A read operations.
   .clka(clk),                     // 1-bit input: Clock signal for port A.
   .ena(rom_enable),                       // 1-bit input: Memory enable signal for port A. Must be high on clock
                                    // cycles when read operations are initiated. Pipelined internally.