Added audio buffer
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ci/woodpecker/push/test-workflow Pipeline was successful
All checks were successful
ci/woodpecker/push/test-workflow Pipeline was successful
It should be working reasonably well at this point
This commit is contained in:
parent
927437e12c
commit
100c8017cc
344
SDVD.xpr
344
SDVD.xpr
@ -44,7 +44,7 @@
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|||||||
<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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||||||
<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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||||||
<Option Name="BoardPart" Val=""/>
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<Option Name="BoardPart" Val=""/>
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||||||
<Option Name="ActiveSimSet" Val="playback_controller_tb"/>
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<Option Name="ActiveSimSet" Val="audio_buffer_tb"/>
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||||||
<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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||||||
<Option Name="ProjectType" Val="Default"/>
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<Option Name="ProjectType" Val="Default"/>
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||||||
<Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../../fpga/vivado-library"/>
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||||||
@ -60,19 +60,19 @@
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|||||||
<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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||||||
<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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||||||
<Option Name="DSABoardId" Val="nexys-a7-100t"/>
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<Option Name="DSABoardId" Val="nexys-a7-100t"/>
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||||||
<Option Name="WTXSimLaunchSim" Val="22"/>
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<Option Name="WTXSimLaunchSim" Val="54"/>
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||||||
<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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||||||
<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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||||||
<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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||||||
<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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||||||
<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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||||||
<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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||||||
<Option Name="WTXSimExportSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="1"/>
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||||||
<Option Name="WTModelSimExportSim" Val="0"/>
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<Option Name="WTModelSimExportSim" Val="1"/>
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||||||
<Option Name="WTQuestaExportSim" Val="0"/>
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<Option Name="WTQuestaExportSim" Val="1"/>
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||||||
<Option Name="WTIesExportSim" Val="0"/>
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<Option Name="WTIesExportSim" Val="0"/>
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||||||
<Option Name="WTVcsExportSim" Val="0"/>
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<Option Name="WTVcsExportSim" Val="1"/>
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<Option Name="WTRivieraExportSim" Val="0"/>
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<Option Name="WTRivieraExportSim" Val="1"/>
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||||||
<Option Name="WTActivehdlExportSim" Val="0"/>
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<Option Name="WTActivehdlExportSim" Val="0"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimRadix" Val="hex"/>
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@ -91,6 +91,20 @@
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<FileSets Version="1" Minor="32">
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<FileSets Version="1" Minor="32">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/design/sdvd_defs.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/design/audio/audio_buffer.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/design/debouncer.sv">
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<File Path="$PPRDIR/design/debouncer.sv">
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<FileInfo>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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@ -112,13 +126,6 @@
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</FileInfo>
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</File>
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</File>
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<File Path="$PPRDIR/design/sdvd_defs.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/design/low_freq_clock_gen.sv">
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<File Path="$PPRDIR/design/low_freq_clock_gen.sv">
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<FileInfo>
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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@ -147,10 +154,19 @@
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<Attr Name="UsedIn" Val="simulation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</FileInfo>
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</File>
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</File>
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<File Path="$PPRDIR/design/audio/pwm.sv">
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<FileInfo>
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<Attr Name="AutoDisabled" Val="1"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="nexys_a7_top"/>
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<Option Name="TopModule" Val="nexys_a7_top"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="VerilogDir" Val="$PPRDIR/design"/>
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</Config>
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</Config>
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</FileSet>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
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@ -266,6 +282,32 @@
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<Option Name="CosimElf" Val=""/>
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<Option Name="CosimElf" Val=""/>
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</Config>
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</Config>
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</FileSet>
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</FileSet>
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<FileSet Name="audio_buffer_tb" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/audio_buffer_tb" RelGenDir="$PGENDIR/audio_buffer_tb">
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<File Path="$PPRDIR/verification/audio/audio_buffer_tb.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="audio_buffer_tb"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
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<Option Name="PamDesignTestbench" Val=""/>
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<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
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<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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<Option Name="PamPseudoTop" Val="pseudo_tb"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="CosimPdi" Val=""/>
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<Option Name="CosimPlatform" Val=""/>
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<Option Name="CosimElf" Val=""/>
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<Option Name="xsim.simulate.runtime" Val="10s"/>
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</Config>
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</FileSet>
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</FileSets>
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</FileSets>
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<Simulators>
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<Simulators>
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<Simulator Name="XSim">
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<Simulator Name="XSim">
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@ -291,7 +333,9 @@
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<Runs Version="1" Minor="22">
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<Runs Version="1" Minor="22">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/nexys_a7_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="true" IncrementalCheckpoint="$PSRCDIR/utils_1/imports/synth_1/nexys_a7_top.dcp" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/synth_1" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024"/>
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2024">
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<Desc>Vivado Synthesis Defaults</Desc>
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</StratHandle>
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<Step Id="synth_design"/>
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<Step Id="synth_design"/>
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</Strategy>
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</Strategy>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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<GeneratedRun Dir="$PRUNDIR" File="gen_run.xml"/>
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@ -301,7 +345,9 @@
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</Run>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" Dir="$PRUNDIR/impl_1" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" LaunchOptions="-jobs 2 " AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024"/>
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="power_opt_design"/>
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@ -317,6 +363,272 @@
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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<RQSFiles/>
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</Run>
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</Run>
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<Run Id="impl_1_copy_1" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_1" ParallelReportGen="true">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
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<Desc>Default settings for Implementation.</Desc>
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</StratHandle>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024" CtrlBit="true">
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<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_1_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="max_paths" Type="" Value="10"/>
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<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_1_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" Version="1" Minor="0">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_1_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="max_paths" Type="" Value="10"/>
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<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_1_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="max_paths" Type="" Value="10"/>
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<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_1_place_report_io_0" Spec="report_io" RunStep="place_design" Version="1" Minor="0">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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</ReportConfig>
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<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_1_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" Version="1" Minor="0">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_1_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" Version="1" Minor="0">
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<ReportConfigOption Name="verbose" Type="" Value="true"/>
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</ReportConfig>
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<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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</ReportConfig>
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<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_1_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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</ReportConfig>
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<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_1_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="max_paths" Type="" Value="10"/>
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||||||
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<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_1_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="max_paths" Type="" Value="10"/>
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<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_1_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" Version="1" Minor="0" IsDisabled="true">
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<ReportConfigOption Name="max_paths" Type="" Value="10"/>
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<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_route_implementation_log_0" Spec="" RunStep="route_design">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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</ReportConfig>
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<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_1_route_report_drc_0" Spec="report_drc" RunStep="route_design" Version="1" Minor="0">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
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<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
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</ReportConfig>
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<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_1_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" Version="1" Minor="0">
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<ReportConfigOption Name="dummy_option" Type="string"/>
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||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_1_route_report_power_0" Spec="report_power" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_1_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_1_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_1_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_1_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_1_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" Version="1" Minor="1">
|
||||||
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_1_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" Version="1" Minor="1">
|
||||||
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_1_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
</ReportStrategy>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles>
|
||||||
|
<RQSFilePath/>
|
||||||
|
</RQSFiles>
|
||||||
|
</Run>
|
||||||
|
<Run Id="impl_1_copy_2" Type="Ft2:EntireDesign" Part="xc7a100tcsg324-1" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_2" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1/impl_1_copy_2" ParallelReportGen="true">
|
||||||
|
<Strategy Version="1" Minor="2">
|
||||||
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2024">
|
||||||
|
<Desc>Default settings for Implementation.</Desc>
|
||||||
|
</StratHandle>
|
||||||
|
<Step Id="init_design"/>
|
||||||
|
<Step Id="opt_design"/>
|
||||||
|
<Step Id="power_opt_design"/>
|
||||||
|
<Step Id="place_design"/>
|
||||||
|
<Step Id="post_place_power_opt_design"/>
|
||||||
|
<Step Id="phys_opt_design"/>
|
||||||
|
<Step Id="route_design"/>
|
||||||
|
<Step Id="post_route_phys_opt_design"/>
|
||||||
|
<Step Id="write_bitstream"/>
|
||||||
|
</Strategy>
|
||||||
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2024" CtrlBit="true">
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Design Initialization" Name="impl_1_copy_2_init_report_timing_summary_0" Spec="report_timing_summary" RunStep="init_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="DRC - Opt Design" Name="impl_1_copy_2_opt_report_drc_0" Spec="report_drc" RunStep="opt_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Opt Design" Name="impl_1_copy_2_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="opt_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Power Opt Design" Name="impl_1_copy_2_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="power_opt_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="IO - Place Design" Name="impl_1_copy_2_place_report_io_0" Spec="report_io" RunStep="place_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Utilization - Place Design" Name="impl_1_copy_2_place_report_utilization_0" Spec="report_utilization" RunStep="place_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Control Sets - Place Design" Name="impl_1_copy_2_place_report_control_sets_0" Spec="report_control_sets" RunStep="place_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="verbose" Type="" Value="true"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_2_place_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Incremental Reuse - Place Design" Name="impl_1_copy_2_place_report_incremental_reuse_1" Spec="report_incremental_reuse" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Place Design" Name="impl_1_copy_2_place_report_timing_summary_0" Spec="report_timing_summary" RunStep="place_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Post-Place Power Opt Design" Name="impl_1_copy_2_post_place_power_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_place_power_opt_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Post-Place Phys Opt Design" Name="impl_1_copy_2_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="phys_opt_design" Version="1" Minor="0" IsDisabled="true">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_2_route_implementation_log_0" Spec="" RunStep="route_design">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="DRC - Route Design" Name="impl_1_copy_2_route_report_drc_0" Spec="report_drc" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Methodology - Route Design" Name="impl_1_copy_2_route_report_methodology_0" Spec="report_methodology" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Power - Route Design" Name="impl_1_copy_2_route_report_power_0" Spec="report_power" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Route Status - Route Design" Name="impl_1_copy_2_route_report_route_status_0" Spec="report_route_status" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Route Design" Name="impl_1_copy_2_route_report_timing_summary_0" Spec="report_timing_summary" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Incremental Reuse - Route Design" Name="impl_1_copy_2_route_report_incremental_reuse_0" Spec="report_incremental_reuse" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Clock Utilization - Route Design" Name="impl_1_copy_2_route_report_clock_utilization_0" Spec="report_clock_utilization" RunStep="route_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Bus Skew - Route Design" Name="impl_1_copy_2_route_report_bus_skew_0" Spec="report_bus_skew" RunStep="route_design" Version="1" Minor="1">
|
||||||
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Timing Summary - Post-Route Phys Opt Design" Name="impl_1_copy_2_post_route_phys_opt_report_timing_summary_0" Spec="report_timing_summary" RunStep="post_route_phys_opt_design" Version="1" Minor="0">
|
||||||
|
<ReportConfigOption Name="max_paths" Type="" Value="10"/>
|
||||||
|
<ReportConfigOption Name="report_unconstrained" Type="" Value="true"/>
|
||||||
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="Bus Skew - Post-Route Phys Opt Design" Name="impl_1_copy_2_post_route_phys_opt_report_bus_skew_0" Spec="report_bus_skew" RunStep="post_route_phys_opt_design" Version="1" Minor="1">
|
||||||
|
<ReportConfigOption Name="warn_on_violation" Type="" Value="true"/>
|
||||||
|
<ReportConfigOutputOption Name="pb" Type="string" Value=""/>
|
||||||
|
<ReportConfigOutputOption Name="rpx" Type="string" Value=""/>
|
||||||
|
</ReportConfig>
|
||||||
|
<ReportConfig DisplayName="implementation_log" Name="impl_1_copy_2_bitstream_implementation_log_0" Spec="" RunStep="write_bitstream">
|
||||||
|
<ReportConfigOption Name="dummy_option" Type="string"/>
|
||||||
|
</ReportConfig>
|
||||||
|
</ReportStrategy>
|
||||||
|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
|
||||||
|
<RQSFiles>
|
||||||
|
<RQSFilePath/>
|
||||||
|
</RQSFiles>
|
||||||
|
</Run>
|
||||||
</Runs>
|
</Runs>
|
||||||
<Board/>
|
<Board/>
|
||||||
<DashboardSummary Version="1" Minor="0">
|
<DashboardSummary Version="1" Minor="0">
|
||||||
|
|||||||
13
bugs.md
Normal file
13
bugs.md
Normal file
@ -0,0 +1,13 @@
|
|||||||
|
## Bugs I Found
|
||||||
|
|
||||||
|
### Audio Buffer
|
||||||
|
- Forgot to assign to a delay counter
|
||||||
|
|
||||||
|
### Debouncer
|
||||||
|
- Logic was fundamentally wrong
|
||||||
|
|
||||||
|
### Display Converter
|
||||||
|
- Found a typo in a single digit
|
||||||
|
|
||||||
|
### Low Freq Clock Gen
|
||||||
|
- Was initially trying to do modulo at max clock speed, failing timing
|
||||||
@ -1,7 +1,144 @@
|
|||||||
|
`include "sdvd_defs.sv"
|
||||||
|
import sdvd_defs::SPEED;
|
||||||
|
|
||||||
//this interfaces with block ram
|
//this interfaces with block ram
|
||||||
module audio_buffer(
|
module audio_buffer(
|
||||||
|
// The clock should be at 48khz
|
||||||
input logic clk, reset,
|
input logic clk, reset,
|
||||||
|
|
||||||
|
|
||||||
|
// Control signals
|
||||||
|
input logic play, stop,
|
||||||
|
input SPEED speed,
|
||||||
|
|
||||||
|
// Whether the current address being read from is in the upper or lower
|
||||||
|
// half of the 2KiB buffer
|
||||||
|
output logic address_half,
|
||||||
|
|
||||||
|
// Whether the audio buffer is currently playing
|
||||||
|
output logic playing,
|
||||||
|
|
||||||
|
// A 16-bit audio sample to output
|
||||||
|
output logic [15:0] sample,
|
||||||
|
|
||||||
|
// Inputs for the memory buffer
|
||||||
|
input logic [10:0] addra,
|
||||||
|
input logic [7:0] dina,
|
||||||
|
input logic clka, ena
|
||||||
);
|
);
|
||||||
|
|
||||||
|
logic [9:0] address;
|
||||||
|
|
||||||
|
// State register
|
||||||
|
logic enb;
|
||||||
|
logic [15:0] doutb;
|
||||||
|
|
||||||
|
// A single bit counter, to avoid feeding samples given the 1 cycle read delay
|
||||||
|
logic delay;
|
||||||
|
|
||||||
|
// The MSB of the address == higher/lower half address
|
||||||
|
assign address_half = address[9];
|
||||||
|
|
||||||
|
always_ff @(posedge clk) begin
|
||||||
|
enb <= 0;
|
||||||
|
if (reset) begin
|
||||||
|
playing <= 0;
|
||||||
|
address <= 0;
|
||||||
|
sample <= 0;
|
||||||
|
delay <= '1;
|
||||||
|
end
|
||||||
|
else if (!playing) begin
|
||||||
|
if (play) begin
|
||||||
|
playing <= 1;
|
||||||
|
delay <= '1;
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
if (stop) begin
|
||||||
|
playing <= 0;
|
||||||
|
// If playback "Stops" then reset the address to a known value, 0
|
||||||
|
address <= 0;
|
||||||
|
delay <= '1;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
// This will overflow to the correct value always
|
||||||
|
address <= address + speed;
|
||||||
|
enb <= 1;
|
||||||
|
// NOTE: I really don't know a good way to generate the load
|
||||||
|
// signal. It maybe could be an inverted 48khz clock?
|
||||||
|
if (delay == 0) begin
|
||||||
|
sample <= doutb;
|
||||||
|
end
|
||||||
|
else begin
|
||||||
|
sample <= '0;
|
||||||
|
delay <= '0;
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
||||||
|
//xpm_memory_sdpram #(
|
||||||
|
// .WRITE_DATA_WIDTH_A(16)
|
||||||
|
//) buffer ();
|
||||||
|
xpm_memory_sdpram #(
|
||||||
|
.ADDR_WIDTH_A(11), // DECIMAL
|
||||||
|
.ADDR_WIDTH_B(10), // DECIMAL
|
||||||
|
.AUTO_SLEEP_TIME(0), // DECIMAL
|
||||||
|
.BYTE_WRITE_WIDTH_A(8), // DECIMAL
|
||||||
|
.CASCADE_HEIGHT(0), // DECIMAL
|
||||||
|
.CLOCKING_MODE("independent_clock"), // String
|
||||||
|
.ECC_BIT_RANGE("7:0"), // String
|
||||||
|
.ECC_MODE("no_ecc"), // String
|
||||||
|
.ECC_TYPE("none"), // String
|
||||||
|
.IGNORE_INIT_SYNTH(0), // DECIMAL
|
||||||
|
.MEMORY_INIT_FILE("none"), // String
|
||||||
|
.MEMORY_INIT_PARAM("0"), // String
|
||||||
|
.MEMORY_OPTIMIZATION("true"), // String
|
||||||
|
.MEMORY_PRIMITIVE("auto"), // String
|
||||||
|
.MEMORY_SIZE(16*1024), // DECIMAL
|
||||||
|
.MESSAGE_CONTROL(0), // DECIMAL
|
||||||
|
.RAM_DECOMP("auto"), // String
|
||||||
|
.READ_DATA_WIDTH_B(16), // DECIMAL
|
||||||
|
.READ_LATENCY_B(1), // DECIMAL
|
||||||
|
.READ_RESET_VALUE_B("0"), // String
|
||||||
|
.RST_MODE_A("SYNC"), // String
|
||||||
|
.RST_MODE_B("SYNC"), // String
|
||||||
|
.SIM_ASSERT_CHK(0), // DECIMAL; 0=disable simulation messages, 1=enable simulation messages
|
||||||
|
.USE_EMBEDDED_CONSTRAINT(0), // DECIMAL
|
||||||
|
.USE_MEM_INIT(1), // DECIMAL
|
||||||
|
.USE_MEM_INIT_MMI(0), // DECIMAL
|
||||||
|
.WAKEUP_TIME("disable_sleep"), // String
|
||||||
|
.WRITE_DATA_WIDTH_A(8), // DECIMAL
|
||||||
|
.WRITE_MODE_B("no_change"), // String
|
||||||
|
.WRITE_PROTECT(1) // DECIMAL
|
||||||
|
)
|
||||||
|
buffer (
|
||||||
|
.doutb(doutb), // READ_DATA_WIDTH_B-bit output: Data output for port B read operations.
|
||||||
|
.addra(addra), // ADDR_WIDTH_A-bit input: Address for port A write operations.
|
||||||
|
.addrb(address), // ADDR_WIDTH_B-bit input: Address for port B read operations.
|
||||||
|
.clka(clka), // 1-bit input: Clock signal for port A. Also clocks port B when
|
||||||
|
// parameter CLOCKING_MODE is "common_clock".
|
||||||
|
|
||||||
|
.clkb(clk), // 1-bit input: Clock signal for port B when parameter CLOCKING_MODE is
|
||||||
|
// "independent_clock". Unused when parameter CLOCKING_MODE is
|
||||||
|
// "common_clock".
|
||||||
|
.dina(dina), // WRITE_DATA_WIDTH_A-bit input: Data input for port A write operations.
|
||||||
|
.ena(ena), // 1-bit input: Memory enable signal for port A. Must be high on clock
|
||||||
|
// cycles when write operations are initiated. Pipelined internally.
|
||||||
|
|
||||||
|
.enb(enb), // 1-bit input: Memory enable signal for port B. Must be high on clock
|
||||||
|
// cycles when read operations are initiated. Pipelined internally.
|
||||||
|
//active high reset
|
||||||
|
.rstb(reset), // 1-bit input: Reset signal for the final port B output register stage.
|
||||||
|
// Synchronously resets output port doutb to the value specified by
|
||||||
|
// parameter READ_RESET_VALUE_B.
|
||||||
|
.wea(ena) // WRITE_DATA_WIDTH_A/BYTE_WRITE_WIDTH_A-bit input: Write enable vector
|
||||||
|
// for port A input data port dina. 1 bit wide when word-wide writes are
|
||||||
|
// used. In byte-wide write configurations, each bit controls the
|
||||||
|
// writing one byte of dina to address addra. For example, to
|
||||||
|
// synchronously write only bits [15-8] of dina when WRITE_DATA_WIDTH_A
|
||||||
|
// is 32, wea would be 4'b0010.
|
||||||
|
);
|
||||||
|
|
||||||
|
endmodule
|
||||||
|
|||||||
122
verification/audio/audio_buffer_tb.sv
Normal file
122
verification/audio/audio_buffer_tb.sv
Normal file
@ -0,0 +1,122 @@
|
|||||||
|
`include "sdvd_defs.sv"
|
||||||
|
import sdvd_defs::SPEED;
|
||||||
|
|
||||||
|
module audio_buffer_tb;
|
||||||
|
logic clk, reset;
|
||||||
|
|
||||||
|
// Control signals
|
||||||
|
logic play, stop;
|
||||||
|
SPEED speed;
|
||||||
|
|
||||||
|
// Whether the current address being read from is in the upper or lower
|
||||||
|
// half of the 2KiB buffer
|
||||||
|
logic address_half;
|
||||||
|
|
||||||
|
// Whether the audio buffer is currently playing
|
||||||
|
logic playing;
|
||||||
|
|
||||||
|
// A 16-bit audio sample to output
|
||||||
|
logic [15:0] sample;
|
||||||
|
|
||||||
|
// Inputs for the memory buffer
|
||||||
|
logic [10:0] addra;
|
||||||
|
logic [7:0] dina;
|
||||||
|
logic clka, ena;
|
||||||
|
|
||||||
|
logic [9:0] counter;
|
||||||
|
|
||||||
|
logic [15:0] test_memory [1023:0];
|
||||||
|
audio_buffer dut(.*);
|
||||||
|
|
||||||
|
// The writer's clock should be much faster than the 48khz buffer clock
|
||||||
|
initial clka = 0;
|
||||||
|
always #5 clka = ~clka;
|
||||||
|
|
||||||
|
|
||||||
|
// An order of magnitude difference is fine
|
||||||
|
initial clk = 0;
|
||||||
|
always #50 clk = ~clk;
|
||||||
|
|
||||||
|
// Reader
|
||||||
|
initial begin
|
||||||
|
`ifdef DEBUG
|
||||||
|
$monitor("PLAYING: %b ADDR: 0x%x DATA: 0x%x WILLDELAY: %b",
|
||||||
|
playing, dut.address, dut.doutb,dut.delay);
|
||||||
|
`endif
|
||||||
|
fork
|
||||||
|
//Reader
|
||||||
|
begin
|
||||||
|
play = 0;
|
||||||
|
stop = 0;
|
||||||
|
clk = 0;
|
||||||
|
reset = 0;
|
||||||
|
speed = 1;
|
||||||
|
@(posedge clk)
|
||||||
|
reset = 1;
|
||||||
|
@(posedge clk)
|
||||||
|
reset = 0;
|
||||||
|
play = 1;
|
||||||
|
@(posedge clk)
|
||||||
|
assert (playing == 1) else $error("Audio buffer not playing");
|
||||||
|
// Wait an extra clock cycle because of the blockmem delay
|
||||||
|
@(posedge clk)
|
||||||
|
// The most basic test we can do here is an incrementing counter,
|
||||||
|
// where the stored sample is the same as the address
|
||||||
|
$display("Running linear test");
|
||||||
|
for (counter = 0; counter != 1023; counter++) begin
|
||||||
|
#1
|
||||||
|
assert ({6'b0, counter} === sample) else
|
||||||
|
$error("Invalid sample, expected 0x%x but found 0x%x",counter,sample);
|
||||||
|
@(posedge clk);
|
||||||
|
end
|
||||||
|
@(posedge clk);
|
||||||
|
$display("Running randomized test");
|
||||||
|
for (counter = 0; counter != 1023; counter++) begin
|
||||||
|
#1
|
||||||
|
assert (test_memory[counter] === sample) else
|
||||||
|
$error("Invalid sample, expected 0x%x but found 0x%x",test_memory[counter],sample);
|
||||||
|
@(posedge clk);
|
||||||
|
end
|
||||||
|
|
||||||
|
end
|
||||||
|
// Writer
|
||||||
|
begin
|
||||||
|
ena = 1;
|
||||||
|
for (int i = 0; i<= 1024; i++) begin
|
||||||
|
addra = i*2;
|
||||||
|
dina = i[7:0];
|
||||||
|
@(posedge clka)
|
||||||
|
addra = i*2+1;
|
||||||
|
dina = i[15:8];
|
||||||
|
@(posedge clka);
|
||||||
|
end
|
||||||
|
wait (address_half==1);
|
||||||
|
// random test, write to lower half of memory
|
||||||
|
for (int i = 0; i< 512; i++) begin
|
||||||
|
addra = i*2;
|
||||||
|
dina = $urandom;
|
||||||
|
test_memory[i][7:0] = dina;
|
||||||
|
@(posedge clka)
|
||||||
|
addra = i*2+1;
|
||||||
|
dina = $urandom;
|
||||||
|
test_memory[i][15:8] = dina;
|
||||||
|
@(posedge clka);
|
||||||
|
end
|
||||||
|
wait (address_half==0);
|
||||||
|
// random test, write to upper half of memory
|
||||||
|
for (int i = 512; i< 1024; i++) begin
|
||||||
|
addra = i*2;
|
||||||
|
dina = $urandom;
|
||||||
|
test_memory[i][7:0] = dina;
|
||||||
|
@(posedge clka)
|
||||||
|
addra = i*2+1;
|
||||||
|
dina = $urandom;
|
||||||
|
test_memory[i][15:8] = dina;
|
||||||
|
@(posedge clka);
|
||||||
|
end
|
||||||
|
end
|
||||||
|
join
|
||||||
|
$finish;
|
||||||
|
end
|
||||||
|
|
||||||
|
endmodule
|
||||||
Loading…
x
Reference in New Issue
Block a user