/****
 * modular_clock_gen.sv - parameterizable clock divider.
 *
 * @author: Waylon Cude, Dilanthi Prentice
 * @date: 6/12/2025
 *
 * */
module modular_clock_gen(
    input clk, reset,
    output logic oclk
);
//parameter has no default because the user should always set it
parameter DIVISOR;

logic [$clog2(DIVISOR)-1:0] counter;

logic set;

always_ff @(posedge clk) begin
    // modular clock has to keep ticking through reset
    // so everything with a synchronous reset actually works
    if (reset && !set) begin
        counter <= DIVISOR-1;
        set <= 1;
    end
    else if (counter == 0)
        counter <= DIVISOR-1;
    else 
        counter <= counter - 1;

    oclk <= counter < (DIVISOR/2);
end

endmodule
