/****
 * pwm.sv - drives the pwm audio output on the FPGA given a single 16-bit
 *          sample. 
 *
 * @author: Dilanthi Prentice, Waylon Cude
 * @date: 6-12-2025
 *
 *
 * */
module pwm(
    input logic clk, reset,
    // Load control signal, if this is high we should load a new sample
    input logic load,
    // The audio sample to play back
    input logic [15:0] sample,
    // The audio output pin
    output wire pwm_pin
);
// This  can't be 16 or we are slowing the audio rate down by a factor of
// 2^5=32
parameter DEPTH=11;

logic [DEPTH-1:0] pulse_counter;
logic [15:0] sample_buffer;
logic should_output;

always_ff @(posedge clk)
begin
    if (reset)
    begin
        pulse_counter <= 0;
        sample_buffer <= 0;
        should_output <= 0;
    end
    
    else
    begin
        if (load)
            sample_buffer <= sample;
        
        pulse_counter <= pulse_counter + 1;

        if (pulse_counter < sample_buffer[15-:DEPTH])
            should_output <= 1;
        else
            should_output <= 0;
    end

end

assign pwm_pin = should_output ? 'z : '0;


endmodule
